The 8-bit breadboarded version of the DrACo/Z80 is a simplified version of the original 16-bit wire-wrapped computer from 2008. Switching to a simplified 8-bit design, along with switching to breadboard construction, allows the computer to be relatively easily completed and tested within a single ten-week term.
Interfacing with peripherals is still possible with the new design. Here is how I/O on Z80 computer systems works…
First, ~CE (Chip Enable) on the Cypress SRAM should be tied directly to the ~MREQ line on the Z80, instead of to Ground. This prevents the memory chip from responding when I/O requests (using the IN and OUT instructions) are used. This is the usual method of wiring ~MREQ. However, some recent versions of the 8-bit system were not intended for use with peripherals, so ~CE was simply tied to Ground on the Cypress chip. Fortunately, re-enabling peripheral compatibility is a one-wire fix.
Bus peripherals interface with the Z80 just like memory chips do: they should respond to reads (from the peripheral) when the ~IORQ and ~RD lines from the Z80 both go low, and they should respond to writes (to the peripheral) when the ~IORQ and ~WR lines from the Z80 both go low. (~RD and ~WR should never both be low at the same time.) Peripherals are also connected to the data bus (for reads and writes), and also read from the lower eight bits of the address bus (A0 through A7).
A typical read cycle (to read data in to the Z80 from a peripheral) would work like this:
- The Z80 places the I/O address (00 through FF) on the lower 8 bits of the address bus.
- The Z80 switches to input (read) mode on the data bus.
- The Z80 lowers the ~IORQ and ~RD lines.
- The Cypress memory chip sees the ~RD line low, but since the ~MREQ line is not also low, it ignores it and stays inactive.
- Any peripherals on the bus see the ~RD line low and the ~IORQ line low. They then (using internal logic) compare the value of the address bus to their internal preset value. If it matches, they place their data (perhaps from a microphone or temperature sensor or voltage sensor etc) onto the data bus.
- After a short delay, the Z80 reads the data from the data bus, and stores it in an accumulator (for an IN instruction) or prepares to send it back out to a memory location (for an INI instruction).
- The Z80 then raises the ~IORQ and ~WR lines. This signals the peripheral that the write cycle is over (and that the peripheral needs to release the data bus now.)
Similarly, a write (to write data from the Z80 to the peripheral) works as follows:
- The Z80 places the I/O address (00 through FF) on the lower 8 bits of the address bus.
- The Z80 places the data to be written onto the data bus.
- The Z80 lowers the ~IORQ and ~WR lines.
- The Cypress memory chip sees the ~WR line low, but since the ~MREQ line is not also low, it ignores it and stays inactive.
- Any peripherals on the bus see the ~WR line low and the ~IORQ line low. They then (using internal logic) compare the value of the address bus to their internal preset value. If it matches, they read the data from the data bus, and do whatever they do with it (output a sound, flash a light, change the state of a relay etc).
- The Z80 then raises the ~IORQ and ~WR lines. This signals the peripheral that the write cycle is over.
If you know that you will only be using one I/O peripheral, you can skip the address-decoding part and simply trigger the peripheral to write to the bus when ~IORQ and ~RD are both low (remember, ~RD and ~WR are named from the Z80’s perspective), and read from the bus when ~IORQ and ~WR are both low.)
