Mad Science : Jacob’s Ladder

Posted on 2012-06-25 by M. Eric Carr

I looked around the lab a few weeks ago and realized something was lacking. I mean, sure, I had some rubidium frequency standards, GPS puzzle boxes, and more PICs than I can shake a stick at, but something was missing — high voltage! (I mean, I do have one high-voltage DC supply, but that’s literally a Fluke.) A Jacob’s Ladder, or traveling-arc display, was clearly called for.

A high-voltage traveling-arc display, commonly known as a Jacob's Ladder. (Click for larger.)

DISCLAIMER: Traveling-arc displays require high voltage, which can injure or kill. The electrodes can get very hot when operating, and could poke you in the eye even when off, if you’re not careful. The transformer is also extremely heavy and could find all kinds of different ways to cause injury.
Don’t try this unless you know what you are doing!

Traveling-arc displays work by ionization of air. Two metal rods are installed in a shallow “V,” with a small gap at the bottom. When a high enough voltage is applied across the rods, the air gap at the base of the “V” breaks down. (The dielectric strength of air is about 3 million volts per meter, or roughly 1mm per kilovolt.) Once the air at the bottom of the V has been broken down and ionized, its conductivity increases quite a bit, allowing a significant current to flow. The air is heated by the power (V^2/R) dissipated in the arc, and begins to rise. Since this ionized air is the path of least resistance, the arc follows the rising air up the “V” until the arc either grows too long to be sustainable at the input voltage, or the top of the “V” is reached.

With sufficient voltage, the arc will remain at the top of the “V” indefinitely. What normally happens, though, is the arc breaks up when the air continues to rise. This raises the voltage between the rods, and the cycle begins again when the air at the bottom of the “V” breaks down once more and another arc rises.

A trip to eBay turned up a good deal on a used 9kV neon sign power supply. Carefully testing it out with a pair of paper clips proved the concept, so the next step was to build a larger “V.” Before I got around to that, though, I was lucky enough to find a 15kV Franceformer neon transformer at Slindy’s Flea Market (near Culpeper, VA). It even came with a bracket and metal “V” — someone else obviously had the same idea. (That’s it in the picture, above.)

A few adjustments to the electrodes later, it’s up and running, and would look right at home in Dr. Frankenstein’s lab. These things are best seen rather than described, though, so here’s a video.

Posted in DoNotTryThisAtHome, High Voltage, Mad Science, Science | Tagged , , | Leave a comment

Z80 delay loops

Posted on 2012-06-01 by M. Eric Carr

Since microprocessors typically run at clock speeds of several MHz, one important software task is to implement delays, to give peripherals (or users) time to respond to data.

There are several methods of producing delays, and each has advantages and disadvantages. One of the simplest methods is the spinloop — so named because the processor simply “spins” through the same small segment of code many times, taking up a given amount of time before continuing on to the next task.

With each instruction taking a fixed amount of time — and a limited number of memory locations available for instructions (65,536 on a 16-bit Z80; 256 on the 8-bit DrACo/Z80) — loops become necessary to implement all but the shortest delays. A counter (typically a register) is set to a certain value at the beginning of the loop, and is then decremented once on each pass through the loop. On each pass, the value in the register is checked to see if it is zero. If so, the processor breaks out of the loop and continues.

Even using 16-bit registers, though, only relatively short delays of perhaps a few hundred thousand clock cycles are possible (since the largest value that can be stored in 16 bits is 65,536.) To get longer delays, multiple loops are nested — one inside the other. This multiplies the loop delays: if both the inner and outer loops have a count of 1,000, the processor will execute the inner 1000-count loop 1000 times, resulting in a much longer delay (the inner loop goes through one million cycles total.)

By varying the values loaded into the registers, the length of the delay can be set to any reasonable value. If using a system clock of 1MHz, a delay of one million instructions would result in a one-second delay — suitable for blinking an LED. A delay of a thousand instructions would result in a one-millisecond delay — a useful interval between sending commands or data to a LCD display.

In Z80 assembly code, a nested delay loop would look something like this :

LD BC, 1000h            ;Loads BC with hex 1000
Outer:
LD DE, 1000h            ;Loads DE with hex 1000
Inner:
DEC DE                  ;Decrements DE
LD A, D                 ;Copies D into A
OR E                    ;Bitwise OR of E with A (now, A = D | E)
JP NZ, Inner            ;Jumps back to Inner: label if A is not zero
DEC BC                  ;Decrements BC
LD A, B                 ;Copies B into A
OR C                    ;Bitwise OR of C with A (now, A = B | C)
JP NZ, Outer            ;Jumps back to Outer: label if A is not zero
RET                     ;Return from call to this subroutine

This will produce a delay roughly proportional to BC * DE. Since both are 16-bit registers, you could set both to 0xFFFF, executing the inner loop up to some 4.2 billion times. Using lower numbers would reduce the delay — using 0x1000 for both as in the example above would be a delay of about 16 million inner loop executions. (The exact formula depends on the number of cycles needed for each instruction — but often, that kind of accuracy isn’t needed.)

The reason for the LD and OR commands is to logically OR the two halves of each 16-bit register together. (It turns out that when you increment or decrement 16-bit registers on the Z80, this doesn’t affect the zero flag, so the JP NZ would go on the information from the last 8-bit operation, which is not what we want. By comparing the two bytes of each register manually, the zero flag is set accordingly, and the JP NZ instruction works as expected.)

 

Posted in Assembly, Coding, Digital, DrACo/Z80, Drexel, EET325 | Leave a comment

Peripheral Interfacing on the 8-bit DrACo/Z80

Posted on 2012-05-30 by M. Eric Carr

The 8-bit breadboarded version of the DrACo/Z80 is a simplified version of the original 16-bit wire-wrapped computer from 2008. Switching to a simplified 8-bit design, along with switching to breadboard construction, allows the computer to be relatively easily completed and tested within a single ten-week term.

Interfacing with peripherals is still possible with the new design. Here is how I/O on Z80 computer systems works…

First, ~CE (Chip Enable) on the Cypress SRAM should be tied directly to the ~MREQ line on the Z80, instead of to Ground. This prevents the memory chip from responding when I/O requests (using the IN and OUT instructions) are used. This is the usual method of wiring ~MREQ. However, some recent versions of the 8-bit system were not intended for use with peripherals, so ~CE was simply tied to Ground on the Cypress chip. Fortunately, re-enabling peripheral compatibility is a one-wire fix.

Bus peripherals interface with the Z80 just like memory chips do: they should respond to reads (from the peripheral) when the ~IORQ and ~RD lines from the Z80 both go low, and they should respond to writes (to the peripheral) when the ~IORQ and ~WR lines from the Z80 both go low. (~RD and ~WR should never both be low at the same time.) Peripherals are also connected to the data bus (for reads and writes), and also read from the lower eight bits of the address bus (A0 through A7).

A typical read cycle (to read data in to the Z80 from a peripheral) would work like this:

  • The Z80 places the I/O address (00 through FF) on the lower 8 bits of the address bus.
  • The Z80 switches to input (read) mode on the data bus.
  • The Z80 lowers the ~IORQ and ~RD lines.
  • The Cypress memory chip sees the ~RD line low, but since the ~MREQ line is not also low, it ignores it and stays inactive.
  • Any peripherals on the bus see the ~RD line low and the ~IORQ line low. They then (using internal logic) compare the value of the address bus to their internal preset value. If it matches, they place their data (perhaps from a microphone or temperature sensor or voltage sensor etc) onto the data bus.
  • After a short delay, the Z80 reads the data from the data bus, and stores it in an accumulator (for an IN instruction) or prepares to send it back out to a memory location (for an INI instruction).
  • The Z80 then raises the ~IORQ and ~WR lines. This signals the peripheral that the write cycle is over (and that the peripheral needs to release the data bus now.)

Similarly, a write (to write data from the Z80 to the peripheral) works as follows:

  • The Z80 places the I/O address (00 through FF) on the lower 8 bits of the address bus.
  • The Z80 places the data to be written onto the data bus.
  • The Z80 lowers the ~IORQ and ~WR lines.
  • The Cypress memory chip sees the ~WR line low, but since the ~MREQ line is not also low, it ignores it and stays inactive.
  • Any peripherals on the bus see the ~WR line low and the ~IORQ line low. They then (using internal logic) compare the value of the address bus to their internal preset value. If it matches, they read the data from the data bus, and do whatever they do with it (output a sound, flash a light, change the state of a relay etc).
  • The Z80 then raises the ~IORQ and ~WR lines. This signals the peripheral that the write cycle is over.

If you know that you will only be using one I/O peripheral, you can skip the address-decoding part and simply trigger the peripheral to write to the bus when ~IORQ and ~RD are both low (remember, ~RD and ~WR are named from the Z80’s perspective), and read from the bus when ~IORQ and ~WR are both low.)

Posted in Assembly, Digital, DrACo/Z80, Drexel, EET325 | Leave a comment

Voltage dividers

Posted on 2012-05-09 by M. Eric Carr

One of the fundamental building blocks of electronics circuits is the voltage divider. By combining two impedances in series, a voltage can be obtained in between these two elements that is some (possibly complex) fraction of the original voltage.

For DC circuits, voltage dividers simply involve two or more resistances — and the math is straightforward:   Vx = Vt * (Rx / Rt), where:

  • Vx is the resulting voltage across one or more elements of the divider;
  • Vt is the total supply voltage across the voltage divider;
  • Rx is the impedance (for DC circuits, the resistance) between the output points; and
  • Rt is the total impedance (for DC, resistance) of all elements of the divider.

As an example, here is a schematic of a basic voltage divider set to produce 3.5V output from a 10V source:

A voltage divider designed to produce 3.5V output, from 10V.

The above formula works well, if there is no significant load on the voltage divider. If the only thing connected to the output was a voltmeter, the output voltage would be very close to 3.5V. If, however, a significant load were attached (say, a light bulb with a 10-ohm resistance), the situation would be quite different…

A "loaded" voltage divider. (Click for larger.)

The voltage divider equation from above is still valid, but the new load resistor must be taken into account. With Rload in parallel with R1, the equivalent resistance of the two can be calculated with the parallel resistor formula: 1/Rt = (1/R1 + 1/Rload). The resulting resistance for the combination is about 9.972 ohms. (R1 hardly matters at all, at this point.)

Substituting this equivalent resistance in creates a very different-looking voltage divider…

The loaded voltage divider, with the R1/Rload combination replaced by its equivalent. (Click for larger.)

Calculating the new, loaded output voltage shows what a difference a low-resistance load makes: Vx = Vt * (Rx/Rt) = 10*(9.972/6509.972) = 0.01532V, or about 15mV.

This dramatic voltage drop occurs because the load resistance is so small in comparison to the resistances used in the voltage divider. One possible solution for this is to use smaller value resistors in the divider, making things more equal:

A "stiff" voltage divider -- using much lower resistances. (Click for larger.)

This helps with the voltage-drop problem somewhat:
Vx = Vt * (Rx/Rt) = 10 * ( 2.593 / 9.093) = 2.85V

There’s a big price to pay for this, though! Even without the load resistor, there is now 1A of current through the voltage divider — at all times. At a supply voltage of 10V, this means that the voltage divider will be dissipating 10 watts even while not powering a load — not exactly energy-efficient. For this reason, voltage dividers are usually used to provide reference voltages for solid-state regulators, instead of being used to actually reduce the main power voltage directly.

 

Posted in EET201, Electronics, Fundamentals | Leave a comment